bge diff

[Brad <brad_(_at_)_comstyle_(_dot_)_com>]

rev 1.5

Put some delay in the loops that poll for MII transaction
completion.  Without this, reading the PHY can hang the bus
on a sufficiently fast CPU.

>From NetBSD

Index: if_bge.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_bge.c,v
retrieving revision 1.39
diff -u -p -r1.39 if_bge.c
--- if_bge.c	10 Dec 2004 02:49:18 -0000	1.39
+++ if_bge.c	10 Dec 2004 04:15:03 -0000
@@ -480,6 +480,7 @@ bge_miibus_readreg(dev, phy, reg)
 		val = CSR_READ_4(sc, BGE_MI_COMM);
 		if (!(val & BGE_MICOMM_BUSY))
 			break;
+		delay(10);
 	}
 
 	if (i == BGE_TIMEOUT) {
@@ -524,6 +525,7 @@ bge_miibus_writereg(dev, phy, reg, val)
 	for (i = 0; i < BGE_TIMEOUT; i++) {
 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 			break;
+		delay(10);
 	}
 
 	if (autopoll & BGE_MIMODE_AUTOPOLL) {